Note: this is an information page, the course is given through LiU's e-learning system lisam

TSEA44 - Computer Hardware - a System on Chip

In this course we will explore the architecture, features and aplication of modern FPGAs (Field Programable Gate Arrays) to hardware accelarated machine learning as an alternative to CPU/GPU hardware. We will learn how to use C-based high-level synthesis to replace traditional Verilog/VHDL RTL design to create fast and efficient hardware accelerators for neural network operators within the machine learning field. The course will cover different hardware optimization strategies and how C-based pragmas are used to control the output generated by high-level synthesis. The VITIS HLS and VIVADO synthesis and implementation tools will target a SoC Zynq FPGA that includes, in addition to the configurable logic, an ARM-based processing system. The course requires previous knowledge on computer architecture, digital design and C/C++ based programming.

The course is given in English.

Lectures

The lectures cover the topics of FPGA technology and architecture, high-level synthesis and neural network inference/training principles and acceleration.

Laboratory work

The course contains hands-on labs that use the PYNQ (Python on Zynq) framework to interface and control the programmable logic. A final project completes the learning objectives by designing a hardware accelerator suitable for large general matrix and vector multiplication in a resource-constrained PYNQ-Z2 board. These type of kernel operators are vital in convolutional, recurrent and fully-connected neural networks.

Course material

Available in lisam

Involved persons

• Jose Nunez-Yanez: examiner, lectures, labs