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TSEK06 - VLSI Design

Chip Design Project - A CDIO course for Y, D, MELE - Periods: VT1 and VT2 - Credits: 12 HP

  • Among the pioneering courses worldwide that comprehensively teach the full design flow—from initial concept to fabricated chip
  • The course has recieved very positive feedback from students who attended the course
  • Highly recommended for students pursuing careers as VLSI circuit design engineers or researchers

Important Information

Group formation and project selection will occur during the second lecture. If you cannot attend, you have two options:

  1. Form a group in advance with fellow students and have them include you on their group list during the selection lecture (ensure they provide your student ID and that the group size does not exceed five members).
  2. Email the head teaching assistant, who will try to assign you to an existing group.

Course Description

A comprehensive introduction to design and fabrication of Very Large Scale Integrated (VLSI) circuits in CMOS technology. The course gives an excellent insight into VLSI chip design and high-performance, low-power circuit techniques. The course supports the CDIO project flow and the LIPS project model to promote teamwork and communication skills required by industry to run large and complex design projects.

Courseflow diagram

Course Format

  • Lectures support the design projects including project descriptions, project planning, and VLSI circuits and chip design techniques in sub-micron CMOS.
  • Labs (a mini-project) introduce the full design flow and CAD tools to be used in the actual projects.
  • Chip design project (the main part of the course): 4-5 students/team design a complete and ready-for-fabrication VLSI chip in a 0.35 µm CMOS process. Projects span digital, mixed-signal, and RF circuit design, with topics varying from year to year. Past project examples include: processor- and ALU-blocks, digital camera sensors, memories, high-speed I/0, advanced timing circuits, ADCs, DACs, filters, radio transceiver blocks, etc.
  • At the end of the course, the designed circuits will be sent for fabrication. The fabricated chips will be available for measurement in a follow-up course, TSEK07: Test and Measurement of Integrated Circuits.

Lab

  • There are six 4-hour lab occasions where you will go through the complete CAD workflow, from high-level modeling to layout and parasitic extraction, and finally the the assembly of a ready-to-fabricate chip.
  • The labs are solved in groups of 2 students. There are multiple rooms booked so that all students will be fit into each session. There is no prior registration for any occasion, just show up on time and start working.
  • The labs are fully described in the laboratory manual that is available for purchase at Bokakademin (the bookshop in Kårallen, see Literature below).
  • To make it easier for yourselves, come well-prepared to each lab, i.e: solve the preparatory excercises and make sure you have read through the lab thoroughly. Also, try to finish the labs as soon as possible as this will help you with your projects. If you find that you are having trouble finishing the labs during the scheduled time, then you may need to work on your own time as well.

Literature

  • Laboratory Manual - TSEK06 VLSI Chip Design Project Available at LiU Servicecenter, House A, entrance 19 C, price 133 SEK (number A2118)
  • Project Guide - TSEK06 VLSI Chip Design Project and TSEK11 Evaluation of an IC
  • Jan M. Rabaey, Digital Integrated Circuits,Prentice-Hall International Edition, ISBN 0-13-394271-6, 1996
  • Behzad Razavi, Design of Analog CMOS Integrated Circuits,McGraw Hill, 2nd Edition, ISBN 978 0 07 252493 2, 2016
  • Jens Lienig, Juergen Scheible, Fundamentals of Layout Design for Electronic Circuits, Springer, eBook ISBN 978-3-030-39284-0, 2020 (Available at LiU Library)

Examination

  • Completed labs
  • Completed chip design and final project report before the project deadline

Grade

Pass or Fail.

Fundamentals of electronics, switching theory, MOS transistors and CMOS technology, radio electronics, digital and analog integrated circuits.

Staff

Available Projects

Link to the course room in Lisam:

Deadlines

   
Jan. 19 2026 Course start.
Jan. 21 2026 Project selection. This will be done at the second lecture.
Feb. 04 2026 Deadline for high-level design and simulation report.
Mar. 11 2026 Deadline for transistor level design and simulation report.
May 06 2026 Layout, LVS, DRC and parasitic simulation should be complete. Only slight touch ups and integration changes may remain.
May 22 2026 Tape out. Hard deadline for delivery of chip GDSII file.
May 29 2026 Deadline for final project report and oral presentation.
   

Chip Photos