Advanced FPGA implementation

The course has two parts. Part 1 runs for the first two weeks and has lectures (T) and guided labs (L). The second part runs for the final two weeks and students work on a project on their own time.

To pass the course you need 1) to pass the online test at the end of week 2 that covers the lectures and guided labs and 2) to pass the main project work that involves getting the system to compute a large matrix multiplication problem correctly in real hardware and be faster than CPU execution.

Content

In this course we will explore initially the architecture and features of modern FPGAs. Then, we will learn how to use C-based high level synthesis as an alternative to traditional Verilog/VHDL RTL design. The course will cover different hardware optimization strategies and how pragmas are used to control the output generated by high level synthesis. The VITIS HLS and VIVADO synthesis and implementation tools will target a SoC Zynq FPGA that includes, in addition to the configurable logic, an ARM-based processing system. The course contains hands-on labs that use the PYNQ (Python on Zynq) framework to interface and control the programmable logic. A final project completes the learning objectives by designing a hardware accelerator suitable for large general matrix multiplications in a resource-constrained PYNQ-Z2 board.

Prerequisites

C++ or C programming, digital systems, computer architecture, some experience with VHDL or Verilog is beneficial.

Schedule

Week 1

Week 2

Week 3 and week 4 own work on main project.